1. Field of the Invention
This invention relates generally to the field of computer processors. More particularly, the invention relates to an apparatus and method for managing a spin transfer torque (STT) memory.
2. Description of the Related Art
Spin-transfer torque (STT) memory cells consists of an access transistor and a magnetic element which store data in the spin direction of each element. Data stored in the magnet is switched following the magnetic tunneling junction effect. Magnetic elements may be fabricated side-by-side with CMOS. STT memories have lower area and comparable read energy compared to other memory technologies but, depending on design, may have higher write energy and/or write times. Unlike CMOS memories, STT memories are non-volatile in that power can be removed and later reapplied without loss of data.
STT memories are “stochastic” devices in that errors can happen at any time. This is similar to errors in conventional CMOS/DRAM memories which are repaired by ECC, but STT memory has design tradeoffs between factors such as write energy, write time, memory size, design complexity, and error rates. In some STT memory configurations, error rates may be higher than with particle strikes. In particular, it may be desirable to accept higher error rates in exchange for improvements in other attributes. STT memories thus rely on ECC for normal operation, and perform a periodic “scrub” scan so recoverable (e.g., single-bit) errors are handled (e.g., repaired) before uncorrectable or undetectable multi-bit errors arise.
STT memory periodic scrubbing scans are superficially similar to DRAM refresh scans, but there are differences. First, a DRAM holds a value reliably for some interval RI, then the value is lost. In contrast, STT memories are always at risk of corruption: a bit value may be corrupted in the first cycle after it is written, and the longer a value is retained, the larger the risk of corruption. Corruption of a specific bit is not predictable, but follows a probability curve. The general goal of STT scrubbing is to find and repair corrupted values before so many bits are corrupted that repair (or even detection) is impossible. More frequent scrubbing improves the odds that all errors can be detected and repaired. The scrub rate is set based on STT technology, temperature, and design-time decisions about acceptable failure rates.
Second, a DRAM refresh always rewrites storage on every refresh. In contrast, STTs need to be checked regularly, but in the absence of errors, no write is required. When an error is detected, it may be a relatively slow and high-energy event; but in practice, designs with good multi-bit reliability also have very low single-bit error rates. Put another way, STT scrubbing is unlike DRAM refresh and so even STTs which have slow and high-energy writes and frequent scrubbing can work well for certain kinds of memories. Further, selective write is easy to implement for STT memories: when an error is detected, correction only needs to write corrected bits, reducing the energy to correct bit errors. Thus scrubbing energy is typically less than DRAM scrubbing energy.
Third, STT memory error rate is strongly dependent on temperature, and the “ideal” scrub rate varies by orders of magnitude. Error rates vary with details of the STT type and the memory cell design, but one sample cell shows a 50 degree Celsius drop in temperature allows about 100,000-fold reduction in scrub rate without reduced reliability.
A similarity to DRAM refresh is scrubbing needs to be timely, else error rates rise. This means in some scenarios that (as with DRAM refresh) STT scrubbing needs priority over ordinary reads and writes or there is data loss. Thus, STT scrubbing may hurt performance of ordinary reads and writes.